Integrated circuit flash memory devices are widely used nonvolatile memory devices that can be electrically erased in large blocks and reprogrammed. As is well known to those having skill in the art, NOR and NAND flash memory devices may be provided. NOR flash memory devices can provide random-access read and programming operations, but generally do not offer arbitrary random-access erase operations. NOR flash memory devices are generally programmed by hot carrier injection. In contrast, NAND flash memory devices generally are accessed for reading and writing by blocks or pages, but can provide relatively low cost and relatively high density. NAND flash memory devices may use Fowler-Nordheim (F-N) tunneling to store data.
A NAND flash memory device is described in U.S. Pat. No. 7,079,437 to Hazama et al. entitled “Nonvolatile Semiconductor Memory Device Having Configuration of NAND Strings With Dummy Memory Cells Adjacent to Select Transistors”. As noted in the Abstract of this patent, a nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together is disclosed. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.
Another NAND-type flash memory cell is described in U.S. Patent Publication 2006/0239077 to Park et al., entitled “NAND Flash Memory Device Having Dummy Memory Cells and Methods of Operating Same”. As noted in the Abstract of this patent publication, a NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.